Delta-sigma analog-to-digital (A/D) converters are widely used in applications that require high resolution at low to medium sampling rates. They lower quantization noise by the feedback loop in conjunction with oversampling. Higher order delta-sigma converters are more effective in suppressing quantization noise, hence requiring a lower oversampling ratio (OSR) for a given signal-to-noise ratio (SNR). However, delta-sigma converters with an order of 2 or more are not inherently stable, and thus require a careful design of the feedback loop for stability.
Delta-sigma converters can be realized in continuous-time form, discrete-time form, or as a hybrid of continuous-time and discrete-time forms. Continuous-time implementations have become popular in recent years due to their higher frequency capability and inherent anti-aliasing property. However, for precision applications, discrete-time switched-capacitor implementations provide much higher accuracy than continuous-time counterparts. Therefore, switched-capacitor implementations are preferred for high-precision, low frequency applications such as sensor interface circuits.
High order delta-sigma A/D converters are desirable because they provide high SNR at a low OSR, but they must be stabilized by at least one zero in the transfer function. Prior art delta-sigma converters employ feedback or feedforward topologies to provide the zeros, for example as described in R. Schreier, et. al., “Understanding Delta-Sigma Data Converters,” Wiley-IEEE Press; 1st edition (Nov. 8, 2004) ISBN-13:978-0471465850, which is hereby incorporated by reference. However, these prior art delta-sigma converters incur a penalty in additional circuitry such as additional digital-to-analog (D/A) converters or another operational amplifier.
It would be desirable to overcome one or more of the deficiencies in existing delta-sigma A/D converters.